Method of forming a multiple fin-pillar capacitor for a high density dram cell
US5907782A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 15, 1998 |
| Grant date | May 25, 1999 |
| Priority date | — |
| Expiry date | Aug 15, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
Abstract
The present invention is a method of manufacturing a high density capacitor for use in semiconductor memories. High etching selectivity between BPSG (borophosphosilicate glass) and CVD-oxide (chemical vapor deposition oxide) is used to fabricate a capacitor with a plurality of horizontal fins. First, a nitride layer is formed on a semiconductor substrate. A stacked layer consists of BPSG and silicon oxide formed on the nitride layer. Then a contact hole is formed in the stacked layer and the nitride layer. A highly selective etching is then used to etch the BPSG sublayers of the stacked layer. Next, a first polysilicon layer is formed in the contact hole and the stacked layer, subsequently, a dielectric layer is formed on the first polysilicon layer. Then, undoped hemispherical-grain silicon (HSG--Si) is formed on the dielectric layer. Next, a portion of the dielectric layer is etched using the HSG--Si layer as a hard mask to expose a portion of the first polysilicon layer. A second polysilicon layer is formed on the HSG--Si layer and the exposed first polysilicon layer. An etching back or CMP is used for planarization. Then photolithography and etching process is used to define th…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.