Translation lookaside buffer supporting multiple page sizes
US5907867A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 1996 |
| Grant date | May 25, 1999 |
| Priority date | — |
| Expiry date | Jun 3, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor integrated circuit device such as a data processing device having a set-associative translation look-aside buffer (TLB). A plurality of address arrays each have a second field for storing the value representing a page size. The values read from the second fields are used to change the range of address comparison by comparators. A plurality of data arrays each have a second field for storing a bit position address designating either an intra-page address or a page number following a page size change. The values read from the second fields of the address arrays are used as the basis for second selectors to select either an address in a predetermined location of an externally input virtual address or the address read from each of the second fields of the data arrays. The selected address is output as a physical address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.