Semiconductor memory device using ferroelectric capacitor
US5909389A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a plurality of memory cells arranged in a matrix format. Each memory cell includes a thin film capacitor with a ferroelectric film and a pair of electrodes opposing each other through the ferroelectric film, and a transfer gate MOS transistor arranged to be connected to the thin film capacitor. The operating voltage value corresponding to the central axis of the polarization hysteresis characteristic curve of the thin film capacitor shifts from 0V by Vf. When no write or read operation is performed for the memory cell, the transistor is turned on, and an adjustment voltage set to be from 0 to 2 Vf is constantly applied across the electrodes of the thin film capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.