Multiway associative external microprocessor cache
US5909694A · kind A · utility
36Cited by
18References
6Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Jun 1, 1999 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache system provides for accessing set associative caches with no increase in critical path delay, for reducing the latency penalty for cache accesses, for reducing snoop busy time, and for responding to MRU misses and cache misses. A multiway cache includes a single array partitioned into a plurality of cache slots and a directory, both directory and cache slots connected to the same data bus. A first cache slot is selected and accessed; and then corresponding data is accessed from alternate slots while searching said directory, thereby reducing the latency penalty for cache access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.