Method and system for layout and schematic generation for heterogeneous arrays
US5910733A · kind A · utility
74Cited by
12References
9Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 12, 1997 |
| Grant date | Jun 8, 1999 |
| Priority date | — |
| Expiry date | Nov 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for defining, placing and routing kernels for a family of integrated circuits is provided. The integrated circuits are defined using repeatable row and column circuit types. Kernels are defined by the intersections of the row and column circuit types in the array. The kernels are placed and routed automatically for each member of the family of integrated circuit arrays, each member being generally characterized by a different size, i.e., a different number of repeatable row or column circuit types.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.