Method for optimization of multi-level interconnect RC delay
US5910747A · kind A · utility
1Cited by
1References
4Claims
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Key dates
| Filing date | Nov 12, 1996 |
| Grant date | Jun 8, 1999 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is herein provided for placing drivers and repeaters along the interconnect so as to optimize interconnection propagation delay with respect to area and time constraints. The method provided optimizes the propagation delay and simplifies the propagation delay determination by first using drivers to divide an interconnect into forkless branches, then linearizing the delay of each branch by placing repeaters along the length of the branches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.