Method and apparatus for single phase clock distribution with minimal clock skew
US5911063A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 1997 |
| Grant date | Jun 8, 1999 |
| Priority date | — |
| Expiry date | Aug 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for generating and distributing a single phase clock in a processor design. A single phase clock signal is generated and applied to a metal grid structure. The metal grid structure is used to distribute the single phase clock signal across an integrated circuit chip. Local clock buffers are used to generate a local clock copy and a local clock complement of the single phase clock signal. Testing is provided with scannable latches by enabling a multiplexer in the latches to select between functional data, scan data, and a reload of latch data. Pipelined globally routed multiplexer scan and hold signals control scan and hold functional modes of the multiplexer. A latch hold function allows the single phase global clock signal to appear functionally as multiple clock frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.