Bitline disturb reduction
US5912837A · kind A · utility
34Cited by
6References
16Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 28, 1996 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Oct 28, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory is described which uses floating gate transistors as memory cells in a memory array. The memory array has blocks of memory cells coupled to a common bitline. A voltage control circuit is described which provides reference voltages for reducing voltage disturbances in non-selected memory cells while selected memory cells are being programmed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.