Process for making a transistor with self-aligned source and drain contacts
US5913136A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 14, 1997 |
| Grant date | Jun 15, 1999 |
| Priority date | — |
| Expiry date | Aug 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a process for making a transistor with self-aligned contact points and comprises the following steps: formation of multiple layers on a substrate (100) and etching of the multiple layers using a first mask, but preserving a column of the multiple layer; formation of lateral spacers on the sides of the column and implantation of impurities; local oxidation of the silicon substrate within the implanted region and elimination of the lateral spacers; deposit of a layer of insulating material (130) surrounding the column; etching of the column in accordance with a second mask to form a grid structure (140) with second sides, and exposing third sides delimiting the active region; formation of self-aligned insulating spacers (142, 143) on the second and third sides, and implantation of the source and drain (150, 152); formation of contact points (160, 162).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.