FPGA repeatable interconnect structure with hierarchical interconnect lines
US5914616A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Feb 26, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17704
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. A combination of single-length lines connecting to adjacent tiles and intermediate-length lines connecting to tiles several tiles away creates an interconnect hierarchy which allows any logic block to be connected to any other logic block, yet also allows for fast paths to both adjacent tiles and tiles some distance away. Longer interconnect lines may be included as a third level of hierarchy to permit interconnection of widely separated tiles. In a preferred embodiment, from a given tile an intermediate-length line connects to the tile three tiles away, then continues and connects to the tile six tiles away. In this embodiment, the intermediate-length line does not connect to the intervening tiles one, two, four, and five tiles away.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.