Computer architecture for the deferral of exceptions on speculative instructions
US5915117A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Oct 13, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The inventive system and method allows for software control of hardware drral of exceptions in speculative operations, and comprises three components. The first component is processor stored information which reflects the code generation strategy of applications and is used by hardware and the operating system to control exception deferral. The second component is processor stored information set by the operating system to specify to hardware which type of faults should be automatically deferred. The third component is further processor stored information which indicates to the hardware to defer certain exception causing aspects of the speculative operation, while performing other non excepting aspects of the speculative operation. The stored information is set after the operating system exception handler has unsuccessfully attempted fault resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.