Semiconductor chip scale package and method of producing such
US5915169A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Dec 23, 1996 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Dec 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.