Multiple part compliant interface for packaging of a semiconductor chip and method therefor
US5915170A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 1997 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Sep 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a multiple part compliant interface for a microelectronic package including the steps of providing a first microelectronic element having electrically conductive parts, providing an array of curable elastomer support pads in contact with the first microelectronic element, curing the curable elastomer support pads while the support pads remain in contact with the first microelectronic element and providing an array of adhesive pads in contact with the support pads, whereby each adhesive pad is disposed over and in substantial alignment with one of the support pads. A second microelectronic element having electrically conductive parts is then assembled in contact with the array of adhesive pads by abutting the second microelectronic element against the array of adhesive pads and compressing the adhesive pads and support pads between the first and second microelectronic elements. The array of adhesive pads are then cured and the electrically conductive parts of the first and second microelectronic elements are interconnected. The array of support pads define channels running between any two adjacent support pads. A flowable curable elastomer encapsulant may be dispo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.