Method for manufacturing a CMOS self-aligned strapped interconnection
US5915199A · kind A · utility
Assignees
Inventor
Key dates
| Filing date | Jun 4, 1998 |
| Grant date | Jun 22, 1999 |
| Priority date | — |
| Expiry date | Jun 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An CMOS interconnection method that permits small source/drain surface areas has been provided. The interconnection is applicable to both strap and via type connections. The surface areas of the small source/drain regions are extended into neighboring field oxide regions by forming a silicide film from the source/drain regions to the field oxide. Interconnections on the same metal level, or to another metal level are made by contact to the silicide covered field oxide. The source/drain regions need only be large enough to accept the silicide film. Transistors with small source/drain regions have smaller drain leakage currents and less parasitic capacitance. A CMOS transistor interconnection apparatus has also been provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.