Emulation methodology for critical dimension control in E-Beam lithography
US5916716A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Mar 13, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S430/143
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Across chip line width variations and other repetitive deviations from the design pattern desired in E-Beam lithography are compensated for by examining each of the regions (i.e., frames, stripes, etc.) of a patterned substrate, determining the amount of deviation for each region, and using the determined regional deviation as a local bias when patterning subsequent substrates. Thus, the E-Beam lithography tool will utilize both global and local biases in order to produce new patterned substrates which lack the deviations found when local bias was not applied. In this way, the root cause of the deviation does not need to be determined. The local bias can be applied directly by modifying the E-Beam lithography system tool commands to provide for patterning wider or thinner lines or to provide for greater or lesser exposure time. Alternatively, the local bias can be applied by varying the emission current of the electron gun for different regions of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.