Photolithographic alignment marks based on circuit pattern feature
US5917205A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1997 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | May 2, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/975
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Photolithographic alignment marks (e.g., mask and measurement overlay marks) are formed of a pattern of very small marks using the design configuration and rule of a circuit pattern feature. A relatively large mark comprising a pattern of small marks modeled after the circuit pattern feature results in an etch rate within the mark area that is substantially the same as the etch rate in the circuit pattern (e.g., cell or peripheral circuit) area. This allows for simultaneous formation of circuit pattern features, and the alignment marks, in a common etching step, while avoiding underetching (shallow etch depth) due to a microloading effect. In this manner, proper formation of readily detectible marks is ensured.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.