Trenched field effect transistor with PN depletion barrier

US5917216A · kind A · utility

Assignee

• SILICONIX INCORPORATED · US

Inventors

• Brian H. Floyd · Sunnyvale, US
• Dorman C. Pitzer · San Jose, US
• Fwu-Iuan Hshieh · Saratoga, US
• Mike F. Chang · Cupertino, US

Key dates

• Filing date: Oct 31, 1996
• Grant date: Jun 29, 1999
• Expiry date: Oct 31, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/235

Abstract

A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.