Fast data alignment display queue structure for image block transfer
US5917506A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 1996 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Dec 5, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A fast data alignment display queue structure for image block transfer comprises a shift circuit, a bit mask, a multi-layer FIFO buffer and a plurality of multiplexers, wherein input data are shifted a desired number of bytes by the shift circuit, and written to the FIFO buffer, and then the data in each level of the FIFO buffer are read by an external DRAM. By using the structure above, a block can be shifted to right or left by filling the data to the FIFO buffer in the sequence started from the first level or in the sequence started from the last level. Therefore, shifting operation for a block can be implemented in different directions without additional transfer logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.