Multi-level DRAM sensing scheme
US5917748A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1998 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Mar 17, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multilevel DRAM sensing structure to detect the level of charge and interpret the digital data from a DRAM cell is disclosed. The multi-level sense amplifier structure has a first and second bit line each having a first and second section. A pair of isolation switch transistors separate the first section of the first bit line from the second section of the first bit line. The first section of the second bit line is separated from the second section of the second bit line by a second pair of isolation switch transistors. A latching sense amplifier has a first input connected to one of the pairs of isolation switch transistors, a second input connected to the other pair of isolation switch transistors, and an output connected to external circuitry. The output will have the digital data represented by the charge in the DRAM cell. A cross coupling capacitor is connected between the first section of the first bit line and the second section of the second bit line to couple a charge shift between the first section of the first bit line and the second section of the second bit line to distinguish the low order bit of the digital data. A control logic section is connected to the DRAM cel…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.