Computer utilizing special micro-operations for encoding of multiple variant code flows
US5918031A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1996 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Dec 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microarchitecture that accommodates divergent instruction sets having different data sizes and addressing modes utilizes a mechanism for translating a generic flow for an instruction into specific operations at run-time. These generic flows use a special class of micro-ops (uops), called "super-uops" (or "Suops)" which are translated into a variable number of regular (i.e., simple) uops. A first-level decoder translates macroinstructions into either simple micro-ops or one or more super-uops which represent one or more sequences of one or more simple uops. A second-level decoder is responsible for converting the super-uops into the appropriate micro-op sequence based upon a set of arguments associated with the super-uop and attributes of the macroinstruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.