System for controlling variable length PCI burst data using a dummy final data phase and adjusting the burst length during transaction
US5918072A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 1995 |
| Grant date | Jun 29, 1999 |
| Priority date | — |
| Expiry date | Sep 18, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A host-bus-to-PCI-bus bridge circuit waits until the PCI-bus clock cycle in which the PCI-bus data transfer corresponding to a current data write access on the originating bus actually takes place, before deciding whether a next data write access is pending on the originating bus and is burstable on the PCI-bus with the current data write access. If so, then the bridge continues the burst with the data of the new data write access. If not, the bridge terminates the PCI-bus burst write transaction by asserting IRDY# and negating FRAME# for the immediately subsequent PCI-bus clock cycle. A final data phase takes place on the PCI-bus in response to these actions, but all data transfer is inhibited because the bridge negates all of the byte-enable signals (BE#(3:0)). An increased likelihood results that successive data write accesses on the originating bus can be collected into a single burst transaction on the PCI-bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.