Parameterized cells for generating dense layouts of VLSI circuits
US5920486A · kind A · utility
133Cited by
8References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 16, 1996 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Aug 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a technique, given a netlist containing a description of the terminal connections and the length and width of each device in a circuit, for automatically producing a layout for each device in that circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.