Rajiv V. Joshi
290Patents
38h-index
190Co-inventors
93Inventor score
Filing activity: Sep 27, 1985 → Apr 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6921982B2 | FET channel having a strained lattice structure along multiple surfaces | Emerging Cross-Sectional Technologies | 270 | Expired |
| US5391510A | Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps | Emerging Cross-Sectional Technologies | 233 | Expired |
| US5955781A | Embedded thermal conductors for semiconductor chips | Electricity | 149 | Expired |
| US6549450B1 | Method and system for improving the performance on SOI memory arrays in an SRAM architecture system | Physics | 143 | Expired |
| US6552398B2 | T-Ram array having a planar cell structure and method for fabricating the same | Electricity | 141 | Expired |
| US5920486A | Parameterized cells for generating dense layouts of VLSI circuits | Electricity | 133 | Expired |
| US5084417A | Method for selective deposition of refractory metals on silicon substrates and device formed thereby | Electricity | 133 | Expired |
| US5585673A | Refractory metal capped low resistivity metal conductor lines and vias | Emerging Cross-Sectional Technologies | 130 | Expired |
| US5300813A | Refractory metal capped low resistivity metal conductor lines and vias | Emerging Cross-Sectional Technologies | 125 | Expired |
| US4647494A | Silicon/carbon protection of metallic magnetic structures | Emerging Cross-Sectional Technologies | 125 | Expired |
| US7380225B2 | Method and computer program for efficient cell failure rate estimation in cell arrays | Physics | 119 | Expired |
| US7681628B2 | Dynamic control of back gate bias in a FinFET SRAM cell | Physics | 118 | Active |
| US7176508B2 | Temperature sensor for high power very large scale integration circuits | Electricity | 113 | Expired |
| US6864540B1 | High performance FET with elevated source/drain region | Electricity | 110 | Expired |
| US8214190B2 | Methodology for correlated memory fail estimations | Physics | 105 | Active |
| US8170857B2 | In-situ design method and system for improved memory yield | Emerging Cross-Sectional Technologies | 103 | Active |
| US7132323B2 | CMOS well structure and method of forming the same | Electricity | 98 | Expired |
| US6034887A | Non-volatile magnetic memory cell and devices | Electricity | 88 | Expired |
| US5403779A | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD | Emerging Cross-Sectional Technologies | 78 | Expired |
| US6323554A | Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD | Emerging Cross-Sectional Technologies | 71 | Expired |
| US5525828A | High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields | Electricity | 67 | Expired |
| US6624459B1 | Silicon on insulator field effect transistors having shared body contact | Electricity | 66 | Expired |
| US7376001B2 | Row circuit ring oscillator method for evaluating memory cell performance | Physics | 66 | Expired |
| US5897370A | High aspect ratio low resistivity lines/vias by surface diffusion | Emerging Cross-Sectional Technologies | 64 | Expired |
| US7301835B2 | Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability | Physics | 59 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.