Emulation system having multiple emulator clock cycles per emulated clock cycle
US5920712A · kind A · utility
70Cited by
47References
32Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 12, 1996 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Nov 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An emulator system allowing a single cycle in a system clock in a user circuit to be emulated in multiple cycles of the emulator system clock. The emulator system provides a unique architecture permitting gates in the emulator to be used to emulate functions in the user circuit without requiring a fixed correspondence between a gate in the emulator and a gate in the user circuit. The emulator system operates in synchronous and asynchronous clock modes and allows the user system clock to be stopped during emulation in selected modes while still maintaining accurate emulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.