System and process for efficiently determining absolute memory addresses for an intermediate code model
US5920722A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 23, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Sep 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and process for efficiently determining absolute addresses for an intermediate code model of an address space are described. A processor interfaces to a main memory comprising a plurality of addressable locations. Each such addressable location is referenced by an absolute address having a maximum size directly proportional to the total number of the addressable locations in the main memory. The absolute addresses form the address space. Source code is supplied specifying program routines which each include at least one reference to an absolute address within the address space. A translator interfaces with the main memory and the storage device. Object code is generated from the source code program routines. Each such absolute address reference in the source code program routines is instantiated with a code sequence for referencing a subset of the address space. Each such absolute address in the address space subset has a total size smaller than the maximum size and is directly proportional to the total number of the addressable locations in the address space subset. The absolute addresses in the address space subset form the intermediate code model. The translated source …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.