Peter C. Damron
30Patents
13h-index
13Co-inventors
74Inventor score
Filing activity: Sep 23, 1997 → Dec 15, 2009
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6918111B1 | System and method for scheduling instructions to maximize outstanding prefetches and loads | Physics | 42 | Expired |
| US6782454B1 | System and method for pre-fetching for pointer linked data structures | Physics | 33 | Expired |
| US6654952B1 | Region based optimizations using data dependence graphs | Physics | 29 | Expired |
| US7039910B2 | Technique for associating execution characteristics with instructions or operations of program code | Physics | 23 | Expired |
| US6578111B1 | Cache memory system and method for managing streaming-data | Physics | 22 | Expired |
| US6668307B1 | System and method for a software controlled cache | Physics | 21 | Expired |
| US8612978B2 | Code execution utilizing single or multiple threads | Physics | 19 | Active |
| US8516465B2 | Register prespill phase in a compiler | Physics | 18 | Active |
| US6427235B1 | Method and apparatus for performing prefetching at the critical section level | Physics | 15 | Expired |
| US6598124B1 | System and method for identifying streaming-data | Physics | 15 | Expired |
| US6687807B1 | Method for apparatus for prefetching linked data structures | Physics | 14 | Expired |
| US5920722A | System and process for efficiently determining absolute memory addresses for an intermediate code model | Physics | 14 | Expired |
| US6718542B1 | Disambiguating memory references based upon user-specified programming constraints | Physics | 13 | Expired |
| US6574713B1 | Heuristic for identifying loads guaranteed to hit in processor cache | Physics | 13 | Expired |
| US6567975B1 | Method and apparatus for inserting data prefetch operations using data flow analysis | Physics | 13 | Expired |
| US6651245B1 | System and method for insertion of prefetch instructions by a compiler | Physics | 11 | Expired |
| US6421826B1 | Method and apparatus for performing prefetching at the function level | Physics | 9 | Expired |
| US6675372B1 | Counting speculative and non-speculative events | Physics | 9 | Expired |
| US6725363B1 | Method for filtering instructions to get more precise event counts | Physics | 8 | Expired |
| US6678796B1 | System and method for scheduling memory instructions to provide adequate prefetch latency | Physics | 7 | Expired |
| US6931510B1 | Method and system for translation lookaside buffer coherence in multiprocessor systems | Physics | 7 | Expired |
| US7502910B2 | Sideband scout thread processor for reducing latency associated with a main processor | Physics | 7 | Expired |
| US6785796B1 | Method and apparatus for software prefetching using non-faulting loads | Physics | 7 | Expired |
| US7137111B2 | Aggressive prefetch of address chains | Physics | 5 | Expired |
| US6167504A | Method, apparatus and computer program product for processing stack related exception traps | Physics | 5 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.