Read-only memory cell arrangement and method for its production
US5920778A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Sep 23, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B20/00
Abstract
In a read-only memory cell arrangement having first memory cells which contain a vertical MOS transistor, and having second memory cells which do not contain vertical MOS transistors, the memory cells are arranged along opposite flanks of strip-shaped parallel insulation trenches (16). The width of the insulation trenches (16) is preferably equal to their separation, so that the memory cell arrangement can be produced with a space requirement of 2F.sup.2 per memory cell, F being the minimum structure size in the respective technology.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.