Chalcogenide memory cell with a plurality of chalcogenide electrodes
US5920788A · kind A · utility
669Cited by
34References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Dec 16, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/90
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A chalcogenide memory cell with chalcogenide electrodes positioned on both sides of the active chalcogenide region of the memory cell. The chalcogenide memory cell includes upper and lower chalcogenide electrodes with a dielectric layer positioned therebetween. The dielectric layer includes an opening defining a pore. A volume of chalcogenide material formed integral to the upper chalcogenide electrode is contained within the pore. The upper and lower chalcogenide electrodes both have greater cross sectional areas than the pore.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.