Apparatus and method for write miss processing in a copy-back data cache with an allocating load buffer and a non-allocating store buffer
US5920889A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1997 |
| Grant date | Jul 6, 1999 |
| Priority date | — |
| Expiry date | Jun 27, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing a write miss signal from a copy-back data cache includes a load-store unit with an allocating load buffer, a non-allocating store buffer, and a priority control circuit to generate write-after-read hazards and read-after-write hazards to preserve the processing priority of entries within the allocating load buffer and the non-allocating store buffer. A prefetch circuit enqueues a prefetch command in the allocating load buffer and a store command in the non-allocating store buffer upon a write miss to the copy-back data cache. Thus, the priority control circuit forces a write-after-read hazard on the store command in the non-allocating store buffer. As a result, the prefetch command in the allocating load buffer secures an allocated line in the copy-back data cache, allowing the store command of the non-allocating store buffer to write data to the allocated line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.