Reference voltage generation scheme for gate oxide protected circuits
US5923211A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | May 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F3/30
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A reference voltage generation circuit is provided for use in gate oxide protected circuits for generating an NMOS reference voltage and PMOS reference voltage in which the NMOS reference voltage is independent of an I/O buffer power supply potential and in which the PMOS reference voltage tracks the supply voltage. The reference voltage generation circuit includes a bandgap voltage reference circuit, a first operational amplifier, a voltage divider and a second operational amplifier. In one embodiment, the NMOS reference voltage is approximately +2.2 volts and is referenced with respect to ground. The PMOS reference voltage is approximately +1.1 volts and referenced with respect to the I/O buffer power supply voltage and the NMOS reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.