Phase shifted design verification routine
US5923566A · kind A · utility
95Cited by
10References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 25, 1997 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Mar 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/705
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A computer-implemented routine that verifies that an existing chip design can be converted to a PSM or reports localized design conflicts based solely on a knowledge of the specific design constraints applied in the targeted PSM design system and without a prior knowledge of specific layout configurations that will cause PSM design errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.