Bist architecture for measurement of integrated circuit delays
US5923676A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Dec 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31858
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A built-in self-test (BIST) method and apparatus for digital integrated circuits (ICs) and for systems including multiple ICs, measures signal propagation delays in combinational and sequential logic, set-up and hold times, and tri-state enable/disable times, from any circuit node to any other circuit node including pin-to-pin and from one IC to another. The IC under test is provided with two test bus conductors passing near every circuit node of interest and connected thereto by switches or buffers. During test, an oscillator is created including the test bus, a constant delay, counters, and a delay path of interest or a reference path. The delay path of interest may include e.g. an analog filter. The oscillation period of the oscillator when the reference path is selected is subtracted from the oscillation period when the oscillator includes a delay path of interest. A circuit automatically accommodates inverting and non-inverting paths. A delay copier copies the delay between any two signal events, without injecting any test signal into the circuit under test (e.g. on-line test), and the delay copy can be measured by selecting it in the oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.