Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing
US5923865A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1995 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Jun 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic emulation system for emulating the operation of a circuit. A uniform routing architecture is provided where a first set of selectors (multiplexers) is coupled to a set of shift registers that are in turn coupled to a second set of selectors. The outputs of the second set of selectors are coupled to the inputs of the logic processors. The arrangement of first selectors coupled to shift registers coupled to second selectors coupled to logic processors ensures that uniform routing exists among all of the logic processors in the emulation system. This, in turn, provides a flat programming model so that compilation steps including technology mapping and scheduling are independent of each other, resulting in faster compile times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.