Fabrication of natural transistors in a nonvolatile memory process

US5923975A · kind A · utility

Assignee

• SGS-Thomson Microelectronics S.A. · IT

Inventor

• Paolo Rolandi · Voghera, IT

Key dates

• Filing date: Jan 16, 1997
• Grant date: Jul 13, 1999
• Expiry date: Jan 16, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/48

Abstract

In a fabrication process of a nonvolatile memory device, natural or low threshold transistors usable in the peripheral circuitry are economically fabricated by exploiting the MATRIX mask that is commonly used for patterning the interpoly dielectric layer for defining the channel length of the natural transistors by patterning the interpoly dielectric layer also over the channel area of the natural transistor, outside the matrix area. The so predefined interpoly dielectric is thereafter exploited as a mask of the polysilicon of a first level during the patterning step of the polysilicon of a second level. Electrical continuity between the polysilicon of the second level and the so patterned gate of polysilicon of the first level are established over the field oxide adjacent to the active area of the natural transistor.