Multi-ported and interleaved cache memory supporting multiple simultaneous accesses thereto
US5924117A · kind A · utility
41Cited by
21References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1996 |
| Grant date | Jul 13, 1999 |
| Priority date | — |
| Expiry date | Dec 16, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed pseudo-, 8-, 16-, or greater, ported cache memory, and associated effective address generation scheme. Based upon either two-port building blocks, or twice as many single-port building blocks, which are interleaved, the cache memory is arranged as a functional equivalent to a true 8-, 16-, or greater ported interleaved cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.