Apparatus and method for pre-verifying a computer instruction set to prevent the initiation of the execution of undefined instructions
US5925125A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 1993 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Jun 24, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Test Operation-Code (TSTOP) instruction pre-verifies the validity of a target instruction op-code prior to execution of the target instruction. The pre-verification function, contained within CPU execution unit microcode, sets a return value in a program status word to indicate one of four conditions: PA1 1. The target instruction is present and operable; PA1 2. The target instruction is present in the computer system, but unavailable on this central processor (e.g. an asymmetric feature). PA1 3. The target instruction is not present in this computer system. PA1 4. The TSTOP op-code is recognized, but the target instruction presence cannot be determined. The return value is testable by the program issuing the TSTOP instruction to determine whether the target instruction should be issued.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.