Semiconductor device in which defects due to LOCOS or heat treatment are suppressed
US5925911A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 1996 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Apr 26, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/668
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device having a concavity formed by LOCOS technique, in which defects induced due to the LOCOS oxidation step or a following heat-treatment step are suppressed, is disclosed. An n.sup.+ type region, the impurity concentration of which is caused to be 1.times.10.sup.19 cm.sup.-3 or more, is formed in an n.sup.- type semiconductor layer. By means of this, defects occur within the n.sup.+ type region or in a proximity of the boundary of the n.sup.+ type region and the n.sup.- type semiconductor layer. The defects trap contaminant impurities taken into the wafer during the manufacturing steps, and cause contaminant impurities existing in the proximity of a concavity of the semiconductor surface to be reduced. As a result thereof, defect occurrence in the proximity of the concavity can be suppressed, and occurrence of leakage and degradation in breakdown voltage between drain and source accompanying defect occurrence in a channel region can be suppressed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.