Merged single polysilicon bipolar NPN transistor
US5925923A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 20, 1997 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Feb 20, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D10/421
Abstract
A merged single polysilicon bipolar NPN transistor, rather than using separate isolation islands for emitter-base and collector contacts, utilizes a single isolation island. This significantly reduces device area because elimination of the second isolation island used in conventional designs reduces the N+ sink to NPN spacing. Buried layer and isolation layer processing proceed in the conventional manner. At sink mask, however, the mask is sized to uncover one end of the main device active region and a sink implant is performed. At base mask, the sink implant remains covered, rather than being exposed as in the conventional flow. At silicide exclusion, the oxide spacer layer is patterned to exclude silicide from the area above the sink implant region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.