Non-equalized digital receiver using block decoding with erasure and error correction
US5926489A · kind A · utility
9Cited by
9References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 22, 1996 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Nov 22, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A communications receiver system is presented for detecting burst errors and providing erasure information to a block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator which includes circuitry to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.