Data processing system and method for maintaining coherency between high and low level caches using inclusive states
US5926830A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 1996 |
| Grant date | Jul 20, 1999 |
| Priority date | — |
| Expiry date | Oct 7, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system and method for maintaining coherency between a high-level (L2) cache and a low-level (L1) cache are disclosed. The L2 (high-level) cache operates in a first mode of operation where a cache line is in a modified and inclusive state, and in a second mode of operation where a cache line is in an invalid and inclusive state. The high-level cache snoops a request from another computing unit for access to data previously stored in the high-level cache. The high-level cache determines if the requested data stored in the high-level cache is invalid or modified, and possibly stored in the low-level cache. If the data is contained in the low-level cache and is modified, the data is returned from the low-level cache to the high-level cache, and from there is written to memory. In the first mode of operation, if no data is returned, and the data in the high-level cache is marked as modified, the data in the high-level cache is written to memory. In the second mode of operation, if no data is returned, the high-level cache does not write any data to memory. In another embodiment, the high-level cache utilizes the state of a line's low-level Inclusive bit when the cache …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.