Patent · US Expired

Combined binary/decimal adder unit

US5928319A · kind A · utility

7Cited by

3References

12Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Wilhelm Haller · Winnenden, DE
Ulrich Krauch · Waldenbuch, DE
Thomas Ludwig · Sindelfingen, DE
Holger Wetter · Holzgerlingen, DE

Key dates

Filing date	Nov 13, 1997
Grant date	Jul 27, 1999
Priority date	—
Expiry date	Nov 13, 2017

Classification

Technology area (CPC G)Physics
CPC primaryG06F7/507
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A combined binary/decimal adder unit reduces the operation delay ine processing binary coded decimal operands and permit an increased cycle rate of a processor unit in which the combined binary/decimal adder unit is utilized. Pre-sums are generated for each decimal digit position in parallel to the generation and distribution of the carries over the total of decimal digit positions of the adder unit. The pre-sums anticipate the carry-in of the decimal positions and the need to perform six corrections after the carry-out signal of the highest decimal digit position has been generated. The carry-out signal of each decimal digit position is used in combination with operation control signals to select the correct pre-sum of the digit position.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.