Method for enhanced peripheral component interconnect bus split data transfer
US5928346A · kind A · utility
8Cited by
17References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 11, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Jun 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A PC bus architecture that is compatible with an industry standard bus architecture and allows devices to transfer data more effeciently. The protocol of the present invention allows a data transaction in which a data transfer request can be made by a bus master device and then queued so that the transaction occurs at a later time allowing the bus to be free for other transactions until the responding device has prepared the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.