Leith L. Johnson
21Patents
11h-index
21Co-inventors
71Inventor score
Filing activity: Apr 29, 1991 → Sep 26, 2007
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6073223A | Memory controller and method for intermittently activating and idling a clock signal for a synchronous memory | Physics | 103 | Expired |
| US5987576A | Method and apparatus for generating and distributing clock signals with minimal skew | Physics | 99 | Expired |
| US6678811B2 | Memory controller with 1X/MX write capability | Physics | 70 | Expired |
| US5287477A | Memory-resource-driven arbitration | Physics | 54 | Expired |
| US5257356A | Method of reducing wasted bus bandwidth due to slow responding slaves in a multiprocessor computer system | Physics | 29 | Expired |
| US5274671A | Use of output impedance control to eliminate mastership change-over delays in a data communication network | Physics | 24 | Expired |
| US5870573A | Transistor switch used to isolate bus devices and/or translate bus voltage levels | Physics | 23 | Expired |
| US5689660A | Enhanced peripheral component interconnect bus protocol | Physics | 21 | Expired |
| US5249297A | Methods and apparatus for carrying out transactions in a computer system | Physics | 21 | Expired |
| US7103793B2 | Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad | Physics | 12 | Expired |
| US5255373A | Decreasing average time to access a computer bus by eliminating arbitration delay when the bus is idle | Physics | 11 | Expired |
| US7103790B2 | Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data | Physics | 10 | Expired |
| US6889335B2 | Memory controller receiver circuitry with tri-state noise immunity | Physics | 9 | Expired |
| US5928346A | Method for enhanced peripheral component interconnect bus split data transfer | Physics | 8 | Expired |
| US6633965B2 | Memory controller with 1×/M× read capability | Physics | 8 | Expired |
| US5961655A | Opportunistic use of pre-corrected data to improve processor performance | Physics | 6 | Expired |
| US7451249B2 | Method and apparatus for direct input and output in a virtual machine environment containing a guest operating system | Physics | 4 | Active |
| US6715014B1 | Module array | Physics | 3 | Expired |
| US8386702B2 | Memory controller | Physics | 1 | Active |
| US7624234B2 | Directory caches, and methods for operation thereof | Physics | 1 | Active |
| US8782779B2 | System and method for achieving protected region within computer system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.