Process for reducing pattern factor effects in CMP planarization
US5928960A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 1996 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Oct 24, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to the present invention, an improved method for planarizing the surface of a dielectric or metal layer in an integrated circuit manufacturing process is disclosed. The dielectric or metal layer to be planarized is selectively patterned and etched over different regions of the surface. The size, shape, density, and depth of the patterns are determined by the pattern factor of the integrated circuit structures underlying the layer to be planarized. Further, by using the pattern factor of the underlying structures to determine the density, size, depth and placement of the surface pattern, the overall planarization process can be improved. Other empirically determined factors, such as material strength, CMP slurry temperature, and pad pressure can also be used to further refine the CMP process. By varying the pattern over the entire surface of the layer to be planarized, the CMP material removal rate can be controlled to achieve a more planar surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.