Single level gate nonvolatile memory device and method for accessing the same

US5929478A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Patrice M. Parris · Phoenix, US
• Yee-Chaung See · Austin, US
• Irenee Pages · Cugnaux, FR
• Juan Buxo · Tempe, US
• Eric Carman · San Francisco, US
• Thierry Sicard · Tournefeuille, FR
• Quang Nguyen · Ramonville-Saint-Agne, FR

Key dates

• Filing date: Jul 2, 1997
• Grant date: Jul 27, 1999
• Expiry date: Jul 2, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B69/00

Abstract

A single level gate NVM device (20) includes a floating gate FET (11) and a capacitor (12) fabricated in two P-wells (27, 28) formed in an N-epitaxial layer (22) on a P-substrate (21). P+ sinkers (29, 31) and N-type buried layers (25, 26) provide isolation between the two P-wells (27, 28). The NVM device (20) is programmed or erased by biasing the FET (11) and the capacitor (12) to move charge carriers onto or away from a conductive layer (36) which serves as a floating gate (14) of the FET (11). Data is read from the NVM device (20) by sensing a current flowing in the FET (11) while applying a reading voltage to the capacitor (12).