Method and apparatus for electrical parasitic measurement of pin grid array
US5929649A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 18, 1996 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Apr 18, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R1/0425
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present method and apparatus for electrically characterizing a pin grid array includes a plurality of conductive caps which may be removably fitted over chosen pins of the pin grid array, and a conductive fixture having a plurality of passages therethrough which correspond to the pins of the pin grid array. The passages are sized so that the caps come in close proximity to the fixture with the fixture so positioned on the pin grid array, while each pin which does not have a cap thereon is not in contact with the fixture but defines an air gap with the fixture. Electrical probing may then take place between the fixture, which connects a number of pins through the caps, and a pin not in contact with the fixture to gain electrical characterization information of the pin grid array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.