Multi-state non-volatile flash memory capable of being its own two state write cache
US5930167A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1997 |
| Grant date | Jul 27, 1999 |
| Priority date | — |
| Expiry date | Jul 30, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5643
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system including an array of flash EEPROM cells arranged in blocks of cells that are erasable together, with individual cells storing more than one bit of data as a result of operating the individual cells with more than two detectable threshold ranges or states. Any portion of the array in which data is not stored can be used as a write cache, where individual ones of the cells store a single bit of data by operating with only two detectable threshold ranges. Data coming into the memory is initially written in available blocks in two states since writing in more than two states takes significantly more time. At a later time, in the background, the cached data is read, compressed and written back into fewer blocks of the memory in multi-state for longer term storage at a reduced cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.