Collar etch method to improve polysilicon strap integrity in DRAM chips

US5930585A · kind A · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Phillipe Coronel · Massy, FR
• Renzo Maccagnan · Muret, FR

Key dates

• Filing date: Dec 20, 1996
• Grant date: Jul 27, 1999
• Expiry date: Dec 20, 2016

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/038

Abstract

In the manufacture of 16 Mbits DRAM chips, a polysilicon strap is used to provide an electrical contact between the drain region of the active NFET device and one electrode of the storage capacitor for each memory cell. The storage capacitor is formed in a trench etch in a silicon substrate which is partially filled with polysilicon. The substrate is conformally coated by a TEOS SiO.sub.2 collar layer having a non-uniform thickness. A chemistry having a high TEOS SiO.sub.2 /Si3N.sub.4 and polysilicon selectively (i.e. which etches TEOS SiO.sub.2 faster than Si.sub.3 N.sub.4 and polysilicon by a factor of at least 6) is used to anisotropically etch the collar layer. C.sub.4 F.sub.8 /Ar/C) mixtures which have selectivities of 9:1 and 15:1 are adequate. When the surface of the Si.sub.3 N.sub.4 pad layer is reached (this can be accurately detected), the etch is continued a short period of time to ensure the complete removal of the horizontal portions of the collar layer, including at the trench bottom, but not the vertical portions in the trench sidewalls.