Branch instruction handling in a self-timed marking system
US5931944A · kind A · utility
25Cited by
6References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Dec 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3816
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An instruction execution pipeline in a computer system having variable-length instructions uses branch prediction to perform self-timed marking of instructions prior to decoding. Branch handling logic is provided in an instruction marking circuit to directly mark a target instruction of a predicted branch as the next instruction to be decoded. Additionally, a branch target FIFO may be used to store information about the location of the target instruction in the instruction stream.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.