Support for out-of-order execution of loads and stores in a processor
US5931957A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 31, 1997 |
| Grant date | Aug 3, 1999 |
| Priority date | — |
| Expiry date | Mar 31, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To support load instructions which execute out-of-order with respect to store instructions, a mechanism is implemented to detect (and correct) the occurrences where a load instruction executed prior to a logically prior store instruction, and where the load instruction received data for the location prior to being modified by the store instruction, and the correct data for the load instruction included bytes from the store instruction. Additionally, to execute store instructions out-of-order with respect to load instructions, a mechanism is implemented to keep a store instruction from destroying data that will be used by a logically earlier load instruction. Further, to support load instructions that are executed out-of-order with respect to each other, a mechanism is implemented to insure that any pair of load instructions (which access at least one byte in common) return data consistent with executing the load instructions in order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.